`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:06:09 09/12/2012
// Design Name:   mux_4_1
// Module Name:   C:/Users/maye/Desktop/taller/lab2/lab3/mux_prueba.v
// Project Name:  lab3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: mux_4_1
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module mux_prueba;

	// Inputs
	reg clk_i;
	reg [3:0] selector_i;
	reg [3:0] contador_i;
	
	
	wire [3:0] dato_o;

	// Instantiate the Unit Under Test (UUT)
	mux_4_1 uut (
		.clk_i(clk_i), 
		.selector_i(selector_i), 
		.contador_i(contador_i), 
		.dato_o(dato_o)
	);
	
	always begin 
	#50 clk_i = ~clk_i;
	end
	always begin 
	#1000 contador_i = contador_i+1;
	end

	initial begin
		// Initialize Inputs
		clk_i = 0;
		selector_i = 1;
		contador_i = 0;

		// Wait 100 ns for global reset to finish
		#1000;
		selector_i = 2;
		#1000;
		selector_i = 4;
		#1000;
		selector_i = 8;
        
		// Add stimulus here

	end
      
endmodule

